Through Wafer Via Process Announced at Semicon West 2006
Silex through wafer 3D interconnect process was presented at the Semicon West 2006 show, July 10-14. The feedback from the MEMS community was remarkably positive. The silicon via process developed by Silex offers sub 50 um via pitch for through wafer connections in up to 600 um thick wafers. The features of the process enables MEMS designs with significantly reduced die size and true “Wafer Level Packaging”. With more than 10 foundry customers using the process today and an extraordinary line-up of potential users, Silex aims at making the process a standard in the MEMS industry. The swift propagation of the technology will be facilitated by reasonable licensing fees as well as technology transfer programs with customers who favor incorporating the technology in their existing manufacturing lines.
